Published On: Thu, Jan 15th, 2015

Orbotech Announces Collaboration with Fraunhofer IZM

SPTS Technologies

Israel’s Orbotech Ltd. an innovator in technologies for both consumer and industrial products, announced that its SPTS Technologies, a supplier of advanced wafer processing solutions for the global semiconductor industry and related markets, is collaborating with Fraunhofer IZM, an international institute specializing in applied and industrial contract research, on the next generation wafer level packaging of microelectronic devices.

SPTS Technologies, an Orbotech company, designs, manufactures, sells, and supports etch, PVD, CVD and thermal wafer processing solutions for the MEMS, advanced packaging, LEDs, high speed RF on GaAs, and power management device markets. With manufacturing facilities in Newport, Wales, Allentown, Pennsylvania, and San Jose, California, the company operates across 19 countries in Europe, North America and Asia-Pacific.

“To meet the technical requirements of future microelectronic products, 3D-IC architectures using through silicon vias (TSVs) are being employed to overcome scaling limits while delivering better device performance, ” stated Kevin Crofton, President of SPTS Technologies and Corporate VP at Orbotech. “SPTS has over 300 DRIE modules being used for advanced packaging applications around the world. Together with Fraunhofer IZM, we aim to develop the techniques needed for cost-effective volume manufacturing of 2.5D and 3D-IC devices.”

For the joint development project, Fraunhofer IZM is using SPTS’ Rapier process module to etch a range of silicon features, such as deep cavities and tapered or vertical TSVs with high aspect ratios. Leveraging its multi-process capability, the Rapier is also used for other 3D processes, including blanket Si etching for via reveal, post grind stress relief and general wafer thinning.

The Rapier carries SPTS’ endpoint detection (EPD) systems: ClaritasTM for etches to stop layers and low exposed areas, and ReViaTM, the industry’s only in-situ EPD for via reveal etching, ensuring repeatable and accurate exposure of TSV tips from the wafer back-side, at via densities as low as 0.01%. With the APM CVD chamber, Fraunhofer IZM is benefiting from SPTS’ ability to deposit PECVD SiN/SiO film stacks at

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